1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to an LCD panel and a simplified method of fabricating the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices express pictures by selectively altering light transmittance characteristics of liquid crystal material within an LCD panel having a plurality of pixels arranged in a matrix. Light transmittance characteristics of the liquid crystal material can be selectively altered with a driving circuit that controls the generation of an electric field through the liquid crystal material (i.e., driving the liquid crystal material).
LCD panels generally include a TFT array substrate joined to, and separated from, a color filter array substrate to form a cell gap. Spacers are distributed within the cell gap to uniformly maintain the distance between the TFT array and color filter array substrates and liquid crystal material is arranged within the cell gap containing the spacers.
The TFT array substrate typically includes gate lines, data lines crossing the gate lines to define pixel areas, switching devices (i.e., TFTs) at the crossings of the gate and data lines, pixel electrodes at each pixel area and connected to each TFT, and an alignment film coated thereon. The gate and data lines receive signals from the driving circuits via corresponding pads. In response to scanning signals transmitted by the gate lines, the TFTs transfer pixel signals from corresponding data lines to corresponding pixel electrodes.
The color filter array substrate typically includes color filters arranged within each pixel area, a black matrix dividing color filters and reflecting external light, a common electrode applying a reference voltage to the pixel areas, and an alignment film coated thereon.
Constructed as described above, the TFT and color filter array substrates are joined together with a sealant and liquid crystal material is injected into the cell gap to complete fabrication of the LCD panel.
The related art process used to fabricate the TFT array substrate described above can be complicated and relatively expensive because it involves a number of semiconductor processing techniques that require a plurality of mask processes. It is generally known that a single mask process requires many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection, etc. To reduce the complexity and cost associated with fabricating TFT array substrates, procedures have been developed to minimize the number of mask processes required. Accordingly, a four-mask process has been developed that removes the necessity of a mask process from a standard five-mask process.
FIG. 1 illustrates a plan view of a TFT array substrate of an LCD device, fabricated using a related art four-mask process. FIG. 2 illustrates a sectional view of the TFT array substrate taken along the I-I′ line shown in FIG. 1.
Referring to FIGS. 1 and 2, the TFT array substrate includes a lower substrate 42 supporting gate lines 2, data lines 4 crossing the gate lines 2 to define a plurality of pixel areas, a gate insulating film 44 between the gate and data lines 2 and 4, a TFT 6 provided each crossing of the gate and data lines 2 and 4, a pixel electrode 18 provided at each pixel area. The TFT array substrate further supports a storage capacitor 20 provided at a region where the pixel electrode 18 overlaps a pre-stage gate line 2, a gate pad 26 connected to the gate line 2, and a data pad 34 connected to the data line 4.
In response to a gate signal applied from a gate line 2, a TFT 6 charges and maintains a pixel signal, applied to a corresponding data line 4, in the pixel electrode 18. Accordingly, each TFT 6 includes a gate electrode 8 connected to a corresponding gate line 2, a source electrode 10 connected to a corresponding data line 4, a drain electrode 12 connected to a corresponding pixel electrode 18, and an active layer 14 overlapping the gate electrode 8. The active layer 14 is overlapped by the data line 4, a lower data pad electrode 36, a storage electrode 22, and defines a channel between the source and drain electrodes 10 and 12 that also overlap the active layer 14. An ohmic contact layer 48 is formed on the active layer 14 and ohmically contacts the data line 4, the source electrode 10, and the drain electrode 12, the lower data pad electrode 36, and storage electrode 22.
Each pixel electrode 18 is connected to the drain electrode 12 of a corresponding TFT 6 via a first contact hole 16 formed through a protective film 50. During operation, an electric field may be generated between the pixel electrode 18 and a common electrode supported by an upper substrate (not shown). The liquid crystal material has a particular dielectric anisotropy. Therefore, in the presence of the electric field, molecules within the liquid crystal material rotate to align themselves between the TFT and color filter array substrates. The magnitude of the applied electric field determines the extent of rotation of the liquid crystal molecules. Accordingly, various gray scale levels of light emitted by a light source (not shown) may be transmitted by a pixel area by varying the magnitude of the applied electric field.
Each storage capacitor 20 consists of a gate line 2 and the portion of the storage electrode 22 overlapping the gate line 2, wherein the two conductors are separated by the gate insulating film 44, the active layer 14, and the ohmic contact layer 48. The pixel electrode 18 is connected to the storage electrode 22 via a second contact hole 24 formed through the protective film 50. Constructed as described above, the storage capacitor 20 allows pixel signals charged at the pixel electrode 18 to be uniformly maintained until a next pixel signal is charged at the pixel electrode 18.
Each gate line 2 is connected to a gate driver (not shown) via a corresponding gate pad 26. Accordingly, the gate pad 26 consists of a lower gate pad electrode 28 and an upper gate pad electrode 32. The lower gate pad electrode 28 is an extension of gate line 2 and is connected to the upper gate pad electrode 32 via a third contact hole 30 formed through the gate insulating film 44 and the protective film 50.
Each data line 4 is connected to a data driver (not shown) via a corresponding data pad 34. Accordingly, the data pad 34 consists of a lower data pad electrode 36 and an upper data pad electrode 40. The lower data pad electrode 36 is an extension of the data line 4 and is connected to the upper data pad electrode 40 via a fourth contact hole 38 formed through the protective film 50.
Having described the TFT array substrate above, a method of fabricating the TFT array substrate according to the related art four-mask process will now be described in greater detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a gate metal pattern, including the gate line 2, the gate electrode 8, and the lower gate pad electrode 28, is formed on the lower substrate 42 in a first mask process.
Specifically, a gate metal layer is formed over the entire surface of the lower substrate 42 in a deposition technique such as sputtering. The gate metal layer consists of a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc. The gate metal layer is then patterned using photolithography and etching techniques in conjunction with an overlaying first mask pattern to provide the aforementioned gate metal pattern.
Referring next to FIG. 3B, a gate insulating film 44 is coated over the entire surface of the lower substrate 42 and on the gate metal pattern. In a second mask process, a semiconductor pattern and a data metal pattern are provided on the gate insulating film 44. The semiconductor pattern consists of the active layer 14 and the ohmic contact layer 48. The data metal pattern consists of the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36, and the storage electrode 22.
Specifically, the gate insulating film 44, a first and a second semiconductor layer, and a data metal layer are sequentially formed over the surface of the lower substrate 42 and on the gate metal pattern by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering. The gate insulating film 44 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer 14 is formed from the first semiconductor layer and typically includes undoped amorphous silicon. The ohmic contact layer 48 is formed from the second semiconductor layer and typically includes n+ doped amorphous silicon. The data metal layer typically includes molybdenum (Mo), titanium (Ti), tantalum (Ta).
A photo-resist film is then formed over the data metal layer and is photolithographically patterned using a second mask pattern. Specifically, the second mask pattern is provided as a diffractive exposure mask having a diffractive exposure region corresponding to a channel region of a subsequently formed TFT. Upon exposure through the second mask pattern and development, a photo-resist pattern is created wherein a portion of the photo-resist film remaining in a region corresponding to the channel region has a lower height relative to portions of the photo-resist film remaining in regions outside the channel region.
Subsequently, the photo-resist pattern is used as a mask to pattern the data metal layer in a wet etching process and to form the aforementioned data metal pattern (i.e., the data line 4, the source electrode 10, the drain electrode 12, and the storage electrode 22), wherein the source and drain electrodes 10 and 12 are connected to each other in a region corresponding to the channel region. Next, the photo-resist pattern is used as a mask to sequentially pattern the first and second semiconductor layers in a dry etching process and form the active layer 14 and the ohmic contact layer 48.
After the active and ohmic contact layers 14 and 48 are formed, the portion of the photo-resist having the relatively lower height is removed from the region corresponding to the channel region in an ashing process. Upon performing the ashing process, the relatively thicker portions of the photo-resist in regions outside the channel region are thinned but, nevertheless, remain. Using the photo-resist pattern as a mask, the portion of the data metal layer and the ohmic contact layer 48 arranged in the channel region are then etched in a dry etching process. As a result, the active layer 14 within the channel region is exposed, the source electrode 10 is disconnected from the drain electrode 12, and the remaining photo-resist pattern is removed in a stripping process.
Referring next to FIG. 3C, the protective film 50 is coated over the entire surface of the lower substrate 42, on the gate insulting film 44, on the data metal pattern, and on the active layer 14. In a third mask process, the first to fourth contact holes 16, 24, 30, and 38, respectively, are formed through the protective film 50 and gate insulting film 44.
Specifically, the protective film 50 is formed over the surface of the lower substrate 42, and on the gate insulting film 44, the data metal pattern, and the active layer 14 by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film 50 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane). A third mask pattern is then arranged over the protective film 50 and the protective film 50 is then patterned by using photolithography and etching processes to thereby define the first to fourth contact holes 16, 24, 30, and 38.
The first contact hole 16 is formed through the protective film 50 to expose the drain electrode 12, the second contact hole 24 is formed through the protective film 50 to expose the storage electrode 22, the third contact hole 30 is formed through the protective film 50 and the gate insulating film 44 to expose the lower gate pad electrode 28, and the fourth contact hole 38 is formed through the protective film 50 to expose the lower data pad electrode 36.
Referring next to FIG. 3D, a transparent conductive pattern including the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40 are formed on the protective film 50 in a fourth mask process.
Specifically, a transparent conductive material is coated over the entire surface of the protective film 50 and in the first to fourth contact holes 16, 24, 30, and 38 by a deposition technique such as sputtering. The transparent conductive material typically includes indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO). In a fourth mask process, the transparent conductive material is patterned using photolithographic and etching techniques to thereby form the aforementioned transparent conductive pattern (i.e., the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40).
Accordingly, the pixel electrode 18 is electrically connected to the drain electrode 12 via the first contact hole 16 while also being electrically connected to the storage electrode 22, via the second contact hole 24. The upper gate pad electrode 32 is electrically connected to the lower gate pad electrode 28 via the third contact hole 30 and the upper data pad electrode 40 is electrically connected to the lower data pad electrode 36 via the fourth contact hole 40.
While the TFT array substrate described above may be formed using a four-mask process that is advantageous over previously known five-mask processes, the four-mask process can still be undesirably complicated and, therefore, costly.
Further, and as mentioned above, LCD panels include spacers for uniformly maintaining a distance between the TFT array and color filter array substrates. Spacers have conventionally been implemented as ball spacers. However, in light of the growing trend in fabricating LCD panels according to liquid crystal dispensing techniques, pattern spacers are increasingly being used to replace ball spacers. Pattern spacers are formed on the TFT or color filter array substrates and overlap areas shielded by the black matrix (i.e., the TFT, the data line, and the gate line) and are conventionally fabricated using mask processes that are not used in forming the TFT array substrate. Thus, when forming the pattern spacers on the TFT array substrate, separate mask processes, unique to the pattern spacers, must be used which undesirably increases the complexity and the cost associated with fabricating an LCD panel.
Lastly, vertical alignment (VA) mode LCD panels include ribs that divide pixel areas into multiple domains. Each rib usually overlaps a pixel electrode to induce different alignment directions of liquid crystal molecules within each domain. Because each pixel area of a VA mode LCD panel has multiple domains of alignment directions, they can display images over a relatively wide viewing angle. Similar to pattern spacers, ribs are conventionally fabricated using mask processes that are not used in forming the TFT array substrate. Thus, when forming the ribs on the TFT array substrate, separate mask processes, unique to ribs, must be used which undesirably increases the complexity and the cost associated with fabricating an LCD panel.
To function properly, the ends of the ribs must be precisely spaced apart from the TFT array substrate when the ribs are formed on the color filter array substrate (or they must be precisely spaced from the color filter array substrate when the ribs are formed on the TFT array substrate). However, the pattern spacers must contact both the TFT and color filter array substrates of the LCD panel. As a result, VA mode LCD panels typically incorporate ribs and pattern spacers having different thicknesses and must, therefore, be undesirably formed in different mask processes, regardless of what substrate the ribs and pattern spacers are formed on. As similarly indicated above, separate implementation of mask processes unique the pattern spacers and ribs undesirably increases the complexity and the cost associated with fabricating a VA mode LCD panel.